An LDMOS device with an increased voltage at source (high side) refers to one whose source cathode is connected with a voltage, such as connected to a same voltage as that of the drain, which is dramatically different from a typical LDMOS device whose source cathode is grounded.
Reference is made to FIG. 1, where an n type LDMOS device with an increased voltage at source (high side) of prior art is shown. An n type buried layer is situated in a p type substrate, and an n type epitaxial layer is situated above on the n type buried layer. The lateral wall of the n type buried layer is in contact with a ring of a p type buried layer, a first p well is situated above the p type buried layer and has a p heavily doped substrate terminal. The first p well, the p type buried layer and the n type buried layer constitutes a bowl shaped isolating ring which isolated the n type epitaxial layer from the p type substrate. A second p well and an n well is situated in the n type epitaxial layer. On the surface of the second p well an n type heavily doped source region and a p type heavily doped body region terminal are situated. In the n type epitaxial layer and on top of the n well, an n type drift region is situated. On the surface of the n type drift region an n type heavily doped drain is situated. On the surface of the n type epitaxial and the n type drift region multiple isolating structures are situated, for isolating the substrate terminal from the drain or the drain from a gate. A gate and a gate oxide layer are situated on the outer side of the source and on top of the second p well, the n type epitaxial layer and n type drift region. A part of the gate is also situated on top of the isolating structure which is on top of the drift region.
The LDMOS device as shown on FIG. 1 can be fabricated by the BCD (bipolar-CMOS-DMOS) technique, and the manufacturing processes can be 0.35 μm. The breakdown voltage of the LDMOS device is subject to two limitations: the first being the breakdown voltage between the n type buried layer and the p type buried layer in the isolating ring structure, the second being the breakdown voltage between the drain and the source. The LDMOS device, due to the limited thickness (less than 4.5 μm) of the n type epitaxial layer and the n type buried layer under the n type epitaxial layer, is unable to withstand voltage in excess of 70v. Even by increasing the length of the n type drift region, the withstand voltage can only be increased up to 50v. Hence, the LDMOS device can only be employed as a power device with an increased voltage at source (high side) whose withstand voltage is 40V.